ADA4610-1_4610-2_4610-4


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SPECIFICATIONS
= ±5 V, V
= 0 V, T
= 25°C, unless otherwise noted.
Table
INPUT CHARACTERISTICS
Offset Voltage
B Grade
ADA4610
ADA4610
0.2
0.4
mV
40°C T
+125°C
0.8
mV
A Grade
0.4
mV
40°C T
+125°C
1.8
mV
Offset Voltage Drift
/T
B Grade (
ADA4610
ADA4610
0.5
µV/°C
A Grade
(SOIC, MSOP, LFSCP)
µV/°C
A Grade
(SOT
µV/°C
Input Bias Current
pA
40°C T
+125°C
nA
Input Offset Current
pA
40°C T
+125°C
nA
Input Voltage Range
2.5
+2.5
Common
Mode Rejection Ratio
CMRR
V to +2.5 V
dB
40°C T
+125°C
Large
Signal Vo
ltage Gain
= 2 k,
OUT
V to +3
ADA4610
40°C T
+125°C
ADA4610
ADA4610
40°C T
+125°C
Input Capacitance
= 0 V
Differen
tial
3.1
Common
Mode
4.8
Input Resistance
= 0 V
OUTPUT CHARACTERISTICS
Output Voltage High
= 2 k
4.85
4.90
40°C T
+125°C
4.6
= 600 
4.6
4.89
40°C T
+125°C
4.05
Out
put Voltage Low
= 2 k
4.95
4.9
40°C T
+125°C
4.75
= 600 
4.9
4.8
40°C T
+125°C
4.4
Short
Circuit Current
±63
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
.5 V to
±18 V






ADA4610
dB
40°C T
+125°C
ADA4610
ADA4610
40°C T
+125°C
Supply Current per Amplifier
OUT
= 0 mA
1.50
1.70
40°C T
+125°C
1.85
mA
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DYNAMIC PERFORMANCE
Slew Rate
= 2 k, A
= +1
Rising
V/µs
Falling
V/µs
Gain Bandwidth Produc
GBP
= 5 mV p
p, R
= 2 k, A
= +100
15.4
MHz
Unity
Gain Crossover
UGC
= 5 mV p
p, R
= 2 k,A
9.3
MHz
Phase Margin
Degrees
3 dB Closed
Loop Bandwidth
3 dB
= +1, V
= 5 mV p
10.6
MHz
Total Harmonic Distortion (T
HD) + Noise
THD + N
1 kHz, A
= 2 k, V
= 1 V rms
0.00025
NOISE PERFORMANCE
Voltage Noise
0.1 Hz to 10 Hz
0.45
µV p
Voltage Noise Density
f = 10 Hz
nV/Hz
f = 100 Hz
8.20
nV/Hz
f = 1 kHz
7.3
nV/Hz
f = 10 kHz
7.30
nV/Hz
�� &#x/MCI; 13; 00;&#x/MCI; 13; 00;1 Guaranteed by design and characterization.
ELECTRICAL CHARACTER
ISTICS
= ±15 V, V
= 0 V, T
= 25°C, unless otherwise noted.
Table
INPUT CHARACTERISTICS
Offs
et Voltage
B Grade (
ADA4610
ADA4610
0.2
0.4
40°C T
+125°C
0.8
A Grade
0.4
40°C T
+125°C
1.8
Offset Voltage Drift
/T
B Grade (
ADA4610
ADA4610
0.5
µV/°C
Grade
(SOIC, MSOP, LFSCP)
µV/°C
A Grade
(SOT
µV/°C
Input Bias Current
40°C T
+125°C
1.50
Input Offset Current
40°C T
+125°C
0.25
Input Voltage Range
12.5
+12.5
Common
Mode Rejection Ratio
CMRR
12.5 V to +12.5 V
40°C T
+125°C
Large Sign
al Voltage Gain
= 2 k, V
OUT
13.5 V
ADA4610
40°C T
+125°C
ADA4610
ADA4610
40°C T
+125°C
Input Capacitance
= 0 V
Different
ial
3.1
Common
Mode
4.8
Input Resistance
= 0 V
�10
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OUTPUT CHARACTERISTICS
Output Voltage High
= 2 k
14.80
14.90
40°C T
+125°C
14.65
= 600 
14.25
14.47
40°C T
+125°C
13.35
Output Voltage Low
= 2 k
14.90
14.85
40°C T
+125°C
14.75
= 600 
14.68
14.60
40°C T
+125°C
14.30
Short
Circuit Current
±79
POWER SUPPLY
Power Supply Rejection Ratio
= ±4.5 V to ±18 V
ADA4610
dB
40°C T
+125°C
ADA4610
ADA4610
40°C T
+125°C
Supply Current per Amplifier
OUT
= 0 mA
1.60
1.85
mA
40°C T
+125°C
2.0
DYNAMIC PERFORMANCE
Slew Rate
SR
= 2 k, A
Rising
V/µs
Falling
V/µs
Gain Bandwi
dth Product
GBP
= 5 mV p
p, R
= 2 k, A
= +100
16.3
MHz
Unity
Gain Crossover
UGC
= 5 mV p
p, R
= 2 k, A
9.3
MHz
Phase Margin
Degrees
3 dB Closed
Loop Bandwidth
3 dB
= +1, V
= 5 mV p
9.5
MHz
Total Harmonic Dis
tortion (THD) + Noise
THD + N
1 kHz, A
= +1, R
= 2 k, V
= 5 V rms
0.00025
NOISE PERFORMANCE
Peak
Peak Voltage Noise
0.1 Hz to 10 Hz bandwidth
0.45
µV p
Voltage Noise Density
f = 10 Hz
nV/Hz
f = 100 Hz
nV/Hz
f = 1 kHz
7.30
nV/Hz
f = 10 kHz
7.30
nV/Hz
�� &#x/MCI; 26; 00;&#x/MCI; 26; 00;1 Guaranteed by design and characterization.
1/ADA4610
2/ADA4610
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ABSOLUTE MAXIMUM RAT
INGS
Table
Supply Voltage
±18 V
Input Voltage
Input Current
±10 mA
Storage Temperature Range
65°C to +150°C
Operating Temperature Range
40°C to +125°C
Junction Temperature Range
65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C
Electrostatic Discharge (H
uman
ody
odel
00 V
Field Induced Charge Device Model (FICDM)
1250
The input pins
have clamp
diodes
connected
to the power supply pins
. Limit
the input current to 10 mA or less whenever input signals exceed the power
supply rail by 0.3 V.
ESDA/JEDEC JS
applicable standard.
JESD22
C101 (ESD FICDM standard of JEDEC) applicab
le standard.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operati
onal
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table
. Thermal Resistance
Package Type
JC
Unit
Lead SOT
219.4
155.6
°C/W
Lead SOIC
°C/W
Lead LFCSP
°C/W
Lead MSOP
°C/W
Lead SOIC
°C/W
Lead LFCSP
3.2
°C/W
is specified for worst
case conditions, that is,
is specified for
device
sol
dered
in
circuit board for surface
mount packages.
ESD CAUTION




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TYPICAL PERFORMANCE
CHARACTERISTICS
= 25°C, unless otherwise noted.
OFFSET VOLTAGE (µV)
NUMBER OF CHANNELS
09646-003
SOIC
Figure
. Input Offset Voltage Distribution
= ±5 V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
TCV
(µV/°C)
NUMBER OF CHANNELS
09646-004
SOIC
Fig
ure
10
09646-005
INPUT OFFSET VO
AGE (µV)
MEAN
MEAN + 3σ
MEAN – 3σ
F楧u牥
11
.⁉npu琠Off獥琠V潬瑡ge⁶献⁃潭m潮
Mod攠
Inp畴
V潬瑡ge
=₱5⁖ⰠR
OFFSET VOLTAGE (µV)
NUMBER OF CHANNELS
09646-006
SOIC
Figure
12
. Input
Offset Voltage Distribution
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
TCV
(µV/°C)
NUMBER OF CHANNELS
09646-007
SOIC
Figure
13
Distribution
= ±15 V
09646-008
INPUT OFFSET VO
AGE (uV)
MEAN
MEAN + 3σ
MEAN – 3σ
F楧u牥
14
.⁉npu琠Off獥琠V潬瑡ge⁶献
Input
Co浭on
M潤e⁖潬瑡ge
㴠±1㔠V
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09646-055
INPUT BIAS CURRENT (pA)
MEAN
MEAN + 3σ
MEAN – 3σ
Figure
Input Bias Current vs.
Common
Mode
Input
Voltage
= ±5 V, R
0.01
0.1
INPUT BIAS CURRENT (pA)
09646-056
+125°C
+25°C
–40°C
SOIC
Figure
16
. Input Bias Current vs. Common
Mode Input Voltage
= ±5 V, R
= 
0.1
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
09646-009
Figure
17
. Input
Bias Current vs. Temperature
= ±5 V
INPUT BIAS CURRENT (pA)
09646-057
MEAN
MEAN + 3σ
MEAN – 3σ
F楧u牥
18
Inpu琠Bi慳⁃urren琠v献⁃潭m潮
M潤e⁉npu琠V潬瑡ge
㴠±1㔠V,
INPUT BIAS CURRENT (pA)
09646-058
0.1
+125°C
+25°C
–40°C
SOIC
Figure
19
. Input Bias Current vs. Common
Mode Input Voltage
= ±15 V, R
= 
0.1
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
09646-012
Figure
20
. Input Bias Current vs. Temperature, V
= ±15 V
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0.1
0.01
0.1
OUT
SOURCE (mA)
(V+ – V
OUT
09646-011
Figure
21
Dropout Voltage
(V+  V
OUT
vs.
OUT
Source, V
= ±5 V
0.1
OUT
SINK (mA)
09646-015
0.1
0.01
(VOUT – V–) (V)
Figure
22
. Dropout Vo
ltage
OUT
vs.
OUT
Sink, V
= ±5 V
FREQUENCY (Hz)
GAIN (dB)
PHASE (Degrees)
09646-016
GAIN
PHASE
Figure
23
. Open
Loop Gain and Phase
Margin
vs. Frequency,
5 V,
= 2 k
0.01
0.1
OUT
SOURCE (mA)
09646-014
0.1
0.01
(V+ – V
OUT
Figure
24
. Dropout Voltage
(V+  V
OUT
vs.
OUT
Source
= ±15 V
0.1
0.01
0.1
0.01
OUT
SINK (mA)
(VOUT – V–) (V)
09646-018
Figure
25
. Dropout Voltage
OUT
vs.
OUT
Sink
= ±15 V
FREQUENCY (Hz)
GAIN (dB)
PHASE (Degrees)
09646-019
GAIN
PHASE
Figure
26
. Open
Loop Gain and Phase
Margin
vs. Fre
quency
= 2 k
= 5 mV
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FREQUENCY (Hz)
GAIN (dB)
09646-017
= +100
= +10
Figure
27
. Closed
Loop Gain vs. Frequency
= ±5 V
0.1
0.01
FREQUENCY (Hz)
OUT
 (Ω)
09646-021
= +100
= +10
Figure
28
. Closed
Loop Output Impedance
OUT
vs. Frequency
= ±5 V
FREQUENCY (Hz)
PSRR (dB)
09646-022
PSRR–
PSRR+
Figure
29
. PSRR vs. Frequency, V
= ±5 V
FREQUENCY (Hz)
GAIN (dB)
09646-020
= +100
= +10
Figure
30
. Closed
Loop Gain vs. Frequency, V
= ±15 V
0.1
0.01
FREQUENCY (Hz)
OUT
 (Ω)
09646-024
= +100
= +10
Figure
31
. Closed
Loop Output Impedance
OUT
vs.
Frequency
= ±15 V
FREQUENCY (Hz)
PSRR (dB)
09646-025
PSRR–
PSRR+
Figure
32
. PSRR vs. Frequency, V
= ±15 V
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FREQUENCY (Hz)
CMRR (dB)
09646-023
Figure
33
. CMRR vs. Frequency
= ±5 V
TIME (µs)
OUTPUT VOLTAGE (V)
09646-027
Figure
34
. Large Signal Transient Response
= ±5 V, A
= +1,
= 2 k
= 100 pF
TIME (µs)
OUTPUT VOLTAGE (mV)
09646-028
Figure
35
. Small Signal Transient Response, V
= ±5 V
= +1,
= 2 k
, C
= 100 pF
FREQUENCY (Hz)
CMRR (dB)
09646-026
Figure
36
. CMRR vs. Frequency, V
= ±15 V
TIME (µs)
OUTPUT VOLTAGE (V)
09646-030
Figure
37
. Large Signal Transient Response
= ±15 V
= +1,
= 2 k
= 100 pF
TIME (µs)
OUTPUT VOLTAGE (mV)
09646-031
Figure
38
. Small Signal Transient Response
5 V, A
= +1,
= 2 k
, C
= 100 pF
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FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/
Hz)
09646-033
Figure
39
. Voltage Noise Density
vs. F
requency
= ±5 V
0.01
0.1
LOAD CAPACITANCE (nF)
OVERSHOOT (%)
09646-034
OS–
OS+
Figure
40
. Overshoot vs. Load Capacitance
= ±5
= +1,
= 2 k
, V
= 100 mV p
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/
Hz)
09646-036
Figure
41
. Voltage Noise Density
vs. Frequency,
= ±15 V
0.01
0.1
LOAD CAPACITANCE (nF)
OVERSHOOT (%)
09646-037
OS–
OS+
Figure
42
. Overshoot vs. Load Capacitance
= ±15 V, A
= +1,
= 2 k
, V
= 100 mV p
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TIME (Seconds)
VOLTAGE (nV)
09646-043
Figure
49
. Voltage Noise, 0.1 Hz to 10 Hz
0.2
0.4
0.6
0.8
1.0
0.1%
0.01%
1.2
1.4
SETTLING TIME (µs)
STEP SIZE (V)
09646-044
Figure
50
–0.5
0.5
1.0
1.5
2.0
2.5
3.0
OUT
TIME (µs)
OUT
09646-200
OUT
= 7.3 × V
Figure
51
. Positive Overload Recovery
09646-047
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
AMPLIFIER (mA)
–40°C
+25°C
+85°C
+125°C
Figure
52
. Supply Current (I
) per Amplifier vs. Supply Voltage (V
Various Temperatures
0.2
0.4
0.6
0.8
1.0
0.1%
0.01%
1.2
1.4
SETTLING TIME (µs)
STEP SIZE (V)
09646-045
Figure
53
–0.5
0.5
1.0
1.5
2.0
2.5
3.0
OUT
TIME (µs)
OUT
09646-201
OUT
= 7.3 × V
Figure
54
. Negative Overload Recovery
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–0.2
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
TIME (µs)
09646-203
AGE (V)
= ±5V
= ±2V
 = 2kΩ
= 100pF
OUTPUT
INPUT
Figure
55
. Positive and Negative Slew Rate (V
= ±5 V, A
= +1, R
= 2 k)
–2.0
–1.5
–1.0
–0.5
0.5
1.0
AGE (V)
TIME (µs)
OUT
09646-202
= ±15V
= ±10V
 = 2kΩ
= 100 pF
Figure
56
. Positive and N
egative Slew Rate (V
= ±15 V, A
= +1, R
= 2 k)
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FUNCTIONAL DESCRIPTI
The
ADA4610
ADA4610
ADA4610
are manufactured
using the Analog Devic
, Inc.
Polar®
rocess, a 36
V
dielectrically
isolated
(DI) process with P
channel JFET technology. The
unique architecture of the
ADA4610
ADA4610
ADA4610
makes it possible to combine high precision and high spe
ed
characteristics into a high voltage, low power op amp.
simplified
schematic
for the
ADA4610
ADA4610
ADA4610
is
shown in
Figure
. The JFET input stage architecture offers
advantages
of low input bias current, high bandwidth, high
gain, low noise
and no phase reversal when
the applied input
signal
exceeds the common
mode
voltage range. The output
stage is rail to rail with high drive characteristics and low
dropout voltage for both si
nking and sourcing currents.
The
ADA4610
ADA4
ADA4610
are
unconditionally
stable for all gain configurations, even with capacitive loads well
in excess of 1 nF.
The devices have
internal protective circuitry
tha
t allows voltages as high as 0.3
V beyond the supplies to be
applied at the input of either t
erminal without causing damage (f
higher input voltage
, refer to the
Input Overvoltage Protection
section
The
ADA4610
ADA4610
B grades achieve less
than 0.4
mV of offset and 4
V/°C of offset drift; these
characteristics
are
usually associated with very high precision
bipolar input amplifiers. The gate current of a typical JFET
doubles every 10°C, resulting in a similar increase in input bias
current over temp
erature. The low power consumption
characteristic of the
ADA4610
ADA4610
ADA4610
minimize
the die temperature, which
warrants low input bias
currents even at elevated ambient temperatures, making the
amplifiers id
eal for applications that require low leakage
specification
without active cooling.
Give special care
to the
printed circuit board (PCB) layout to minimize leakage currents
between PCB traces. Improper layout and board handling may
generate leakage curren
ts exceeding the bias currents of the
erational
amp
lifier
The
ADA4610
ADA4610
ADA4610
are
fully specified with
supply voltages from
5 V to ±15 V over the extended
industrial
temperature range of
40°C to +125°C.
The
ADA4610
is
available in an 8
lead SOIC.
The
ADA4610
is
available
in
lead MSOP,
an
lead SOIC
, and
an
lead LFCSP
he
ADA4610
is
availabl
in a 14
lead SOIC
and
lead
LFCSP
All these packages are surface
mount type.

Q28
Q27
OUT
09646-054
Q15
Q14
Q13
Q17
Q16
Q23
Q29
Q30
Q25
Q24
Q18
Q12
DE1
IN+
IN–
DE5
DE6
DE3
DE2
DE4
Figure
57
. Simplified Schematic
1/ADA4610
2/ADA4610
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APPLICATION
INFORMATION
INPUT OVERVOLTAGE PR
OTECTION
The
ADA4610
ADA4610
ADA4610
have internal protective
circuitry that
allows voltages as high as 0.3
V beyond the supplies
to be applied at the input of either terminal without causing
damage. For higher in
put voltages, a series resistor
is necessary
to limit the input
current.
where:
is the input voltage
is
the voltage of
either V+ or V.
is the series resistor.
With a very low bias current of 1
.5 nA up to 125°C, higher
resistor values can be used in s
eries with the inputs. A 5 k
resistor protects the inputs from voltages as high as 25 V
beyond the supplies and adds less than 10 µV to the offset.
PEAK DETECTOR
ADA4610-1/
ADA4610-2
ADA4610-4
ADA4610-1/
ADA4610-2
ADA4610-4
50pF
1µF
+PEAK
09646-149
Figure
58
1/2
09646-154
ADA4610-1/
ADA4610-2
ADA4610-4
Figure
59
Equivalent Preamplifier Photodiode Circuit
A larger signal bandwidth can be attained at the expense of
additional
output noise.
The total input capacitance (C
) consists
of
the sum of the diode capacitance (typically 3
pF to 4
pF) and
the amplifier
input capacitance (
10
pF), which includes external
parasiti
c capacitance.
creates a zero
in the frequency response
that can lead to an unstable system. To ensure stability and
optimize the bandwidth of the signal,
place
a capacitor in the
feedback loop of the circuit shown in
Figure
The capacitor
creates a pole
and yields
a bandwidth
with a
corner frequency
1/(2(
where:
is the feedback resistor.
is the feedback capacitor.
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For ex
ample, if I
is 100 µA and a 10 V output voltage is
needed
must
be 100 k.
The resistance of the photodiode (
is a
junction resistance
(see
Figure
A typical value for
is 1000
M. Because
the circuit
behavi
or is not impacted by the effect of the junction resistance.
The maximum signal bandwidth is
MAX
where
is the unity
gain frequency of the
op amp
Calculate
R
C
C
T
F
2
where
is the unity
gain frequency of the op am
p, and it achieves
a phase margin, 
, of approximately 45°.
Increase the C
value to obtain a
higher phase margin. Se
tting
to twice the previous value yields approximately
= 65° and a
maximal flat frequency response, but it reduces
the maximum
signa
l bandwidth by 50%.
Using the previous parameters with a
pF, the signal
bandwidth is approximately
Hz.
COMPARATOR OPERATION
Although
op amps
are quite different from comparators,
occasionally an unused section of a dual or a quad
op amp
can
be used as a comparator; however, this is not recommended for
rail
rail output op amp
. For rail
rail output op amps, the
output
stage is generally a ratioed current mirror with bipolar or
MOSFET
transistors. With the
device
operating
in
open
mode
, the second stage
increases the current drive to the ratioed
mirror to close the loop. However,
the second stage
cannot
close
the loop
, which results in an increase in supply current.
With
the
ADA4610
ADA4610
ADA4610
op amps configured
as compar
ators
, the supply current can be significantly higher
(see
Figure
for
the
supply current vs.
the
supply voltage
for
the
ADA4610
).
Configuring a
n unused section as a voltage follower
with the noninverting input connected to a voltage within the
input voltage range
is recommended
. The
ADA4610
ADA4610
ADA46
have
a unique output stage design
that re
duces the
excess supply current
but does not
entirely
eliminate this effect
when the op amp is operating
in
open
oop
mode
09646-053
CHANNELS (mA)
COMPARATOR, V
OUT
= HIGH
COMPARATOR, V
OUT
= LOW
FOLLOWER
Figure
60
Supply Current
vs. Supply Voltage
or the
ADA4610
Only
1/ADA4610
2/ADA4610
��Rev.
| Page
of
OUTLINE DIMENSIONS
Figure
61
Lead Standard Small Outli
ne Package [SOIC_N]
Narrow Body
8)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure
62
Lead Mini Small Outline Package [MSOP]
(RM
8)
��Rev.
| Page
of
T
J
S
M
5
0
E
A
T
I
N
G
P
L
A
N
E
.
9
0
B
S
C
0
.
9
5
B
S
C
0
.
6
0
B
S
C
1
2
3
4
.
0
0
2
.
9
0
2
.
8
0
.
0
0
2
.
8
0
2
.
6
0
.
7
0
1
.
6
0
1
.
5
0
.
3
0
1
.
1
5
0
.
9
0
.
1
5
M
A
X
0
.
0
5
M
I
N
.
4
5
M
A
X
0
.
9
5
M
I
N
.
2
0
M
A
X
0
.
0
8
M
I
N
.
5
0
M
A
X
0
.
3
5
M
I
N
.
5
5
0
.
4
5
0
.
3
5
1
1
Figure
63
Lead Small Outline Transistor Package [SOT
23]
(RJ
5)
Dimensions shown in millim
2.54
2.44
2.34
0.50
0.40
0.30
VIEW
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
TING
PLANE
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF
0.20 MIN
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PIN 1
INDIC
(R 0.20)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
12-03-2013-
PKG-004371
3.10
3.00 SQ
2.90
Figure
64
Lead
Lead Frame Chip
Scale Package [LFCSP]
3
Body
and 0.75 mm Package Height
1/ADA4610
2/ADA4610
��Rev.
| Page
of
CONTROLLING DIMENSIONS
ARE IN MILLIMETERS; INCH DIMENSIONS
(IN
ARENTHESES)
ARE ROUNDED-OFF MILLIMETER EQUI
ALENTS FOR
REFERENCE ON
ARE NOT
APPROPRI
TE FOR USE IN DESIGN.
COMPLIANT
O JEDEC S
ANDARDS MS-012-AB
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
TING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARIT
0.10
Figure
65
. 14
Lead Standard Small Outline Package [
SOIC_N]
Narrow Body
14)
4.10
4.00 SQ
3.90
0.35
0.30
0.25
2.25
2.10 SQ
1.95
0.65
BSC
BOT
OM VIEW
VIEW
0.70
0.60
0.50
TING
PLANE
0.05 MAX
0.02 NOM
0.203 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDIC
0.80
0.75
0.70
COMPLIANT
JEDEC STANDARDS MO-220-WGGC.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
04-15-2016-A
PKG-004025/5
PIN 1
INDIC
OR AREA OPTIONS
DETAIL A
(JEDEC 95)
EXPOSED
PAD
Figure
66
. 16
Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body
and 0.75 mm Package Height
(CP
16
23)
��Rev.
| Page
of
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding
ADA4610
1ARZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
1ARZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4
610
1ARZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
1BRZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
1BRZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
1BRZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
1ARJZ
40°C to +125°C
Lead Small Outline Transistor Package [SOT
23]
A37
ADA4610
1ARJZ
40°C to +125°C
Lead Small Outline Transistor Package [SOT
23]
A37
ADA4610
1ARJZ
40°C to +125°C
Lead Small Outline Transistor Package [SOT
23]
A37
ADA4610
2ACPZ
40°C to +125°C
Lead Lead Frame Chip Scale Package [LFCSP]
A2U
ADA4610
2ACPZ
40°C to +125°C
Lead Lead Frame Chip Scale Packag
e [LFCSP]
A2U
ADA4610
2ARMZ
40°C to +125°C
Lead Mini Small Outline Package [MSOP]
A2U
ADA4610
2ARMZ
40°C to +125°C
Lead Mini Small Outline Package [MSOP]
A2U
ADA4610
2ARMZ
40°C to +125°C
Lead Mini Small Outline Package [
MSOP]
A2U
ADA4610
2ARZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
2ARZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
2ARZ
40°C to +125°C
Lead Standard Small Outline Package [SO
IC_N]
ADA4610
2BRZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
2BRZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
2BRZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N
ADA4610
4ARZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
4ARZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_N]
ADA4610
4ARZ
40°C to +125°C
Lead Standard Small Outline Package [SOIC_
ADA4610
4ACPZ
40°C to +125°C
Lead Lead Frame Chip Scale Package [LFCSP]
ADA4610
4ACPZ
40°C to +125°C
Lead Lead Frame Chip Scale Package [LFCSP]
�� &#x/MCI; 13; 00;&#x/MCI; 13; 00;1 Z = RoHS Compliant Part.
2011
2016
Analo
g Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09646
5/16(G)
Low Noise, Precision, Rail
Rail Output,
JFET
Single/
Dual/Quad Op Amps
ADA4610
ADA4610
ADA4610
Rev.
Document Feedback
Information furnished by Analog
Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change with
out notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106,
Norwood, MA 02062
910
6, U.S.A.
Tel: 781.329.4700
2011
2016
Analog Devices, Inc. All rights reserved.
Technical Support
www.an
alog.com
09646-002
OUT
–IN
+IN
OUT B
–IN B
+IN B
ADA4610-2
VIEW
(Not to Scale)
able
Related
Prec
ision JFET
Operational Amplifiers
Single
Dual
Quad
AD8510
AD8512
AD8513
AD8610
AD8620
Not applicable
AD820
AD822
AD824
ADA4627
ADA4637
Not applicable
Not applicable
Not applicable
ADA4001
Not applicable
Rev. G | Page 2 of 25
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 4
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 10
Comparative Voltage and Variable Voltage Graphs ............... 16
Functional Description .................................................................. 19
Applications Information .............................................................. 20
Input Overvoltage Protection ................................................... 20
Peak Detector .............................................................................. 20
Current to Voltage (I to V) Conversion Applications ........... 20
Comparator Operation .............................................................. 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 25
REVISION HISTORY
5/2016„Rev. F to Rev. G
Changed CP-8-20 to CP-8-21 ...................................... Throughout
Changes to Figure 23 Caption and Figure 26 Caption .............. 13
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
1/2016„Rev. E to Rev. F
Added 5-Lead SOT-23 ....................................................... Universal
Changed CP-8-9 to CP-8-20 ........................................ Throughout
Change to Features Section ............................................................. 1
Added Figure 3 and Table 7; Renumbered Sequentially ............. 8
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 25
4/2015„Rev. D to Rev. E
Added ADA4610-1 ............................................................. Universal
Added 16-Lead LFCSP_WQ ............................................. Universal
Rev. G | Page 16 of 25
COMPARATIVE VOLTAGE AND VARIABLE VOLTAGE GRAPHS
09646-205
0.00001
0.0001
0.001
0.01
0.1
0.01
0.1
THD + N (%)
AMPLITUDE (V rms)
= ±5V
= 2k
= 1kHz
80kHz FILTER
Figure 43. THD + N vs. Amplitude, V
= ±5 V
09646-204
0.00001
0.0001
0.001
0.01
0.1
10
10k
100k
THD + N (%)
FREQUENCY (Hz)
80kHz BAND-PASS FILTER
500kHz BAND-PASS FILTER
= ±5V
= 1.5V rms
Figure 44. THD + N vs. Frequency, V
= ±5 V
–120
–140
–160
–100
1001k10k100k
FREQUENCY (Hz)
CHANNEL
SEPARATION (dB)
09646-039
Figure 45. Channel Separation vs. Frequency
0.1
0.01
0.001110
AMPLITUDE (V rms)
THD + N (%)
0.00001
0.0001
0.001
0.01
0.1
09646-040
= ±15V
= 2k
= 1kHz
80kHz FILTER
Figure 46. THD + N vs. Amplitude, V
= ±15 V
09646-141
0.00001
0.0001
0.001
0.01
0.1
10
100
10k
100k
THD + N (%)
FREQUENCY (Hz)
= ±15V
= 5V rms
80kHz BAND-PASS FILTER
500kHz BAND-PASS FILTER
Figure 47. THD + N vs. Frequency, V
= ±15 V
–12
–16
00.10.20.30.40.50.60.70.80.91.0
TIME (ms)
VOLTAGE (V)
09646-042
OUTPUT
INPUT
Figure 48. No Phase Reversal, V
= ±15 V, A
= +1, R
= 2 k, C
= 100 pF
Rev. G | Page 9 of 25
OUT A
–IN A
+IN A
OUT D
–IN D
+IN D
+IN B
+IN C
–IN B
–IN C
OUT B
OUT C
ADA4610-4
TOP VIEW
(Not to Scale)
09646-106
Figure 7.
ADA4610-4
Pin Configuration, 14-Lead SOIC (R Suffix)
–IN D
+IN D
9+IN C
–IN A
+IN A
+IN B
TOP
VIEW
ADA4610-4
NOTES
1.NIC = NOT INTERNALLY CONNECTED.
.THE EXPOSED PAD MUST BE CONNECTED TO V–.
09646-107
Figure 8.
ADA4610-4
Pin Configuration, 16-Lead LFCSP (CP Suffix)
ADA4610-4
Pin Function Descriptions, 14-Lead SOIC and 16-Lead LFCSP
Pin No.
14-Lead SOIC 16-Lead LFCSP Mnemonic Description
OUT A Output Channel A.
ŠIN A Inverting Input Channel A.
+IN A Noninverting Input Channel A.
4 3 V+ Positive
Voltage.
Noninverting Input Channel B.
Inverting Input Channel B.
OUT B Output Channel B.
OUT C Output Channel C.
ŠIN C Inverting Input Channel C.
+IN C Noninverting Input Channel C.
11 10 VŠ Negative
Voltage.
+IN D Noninverting Input Channel D.
ŠIN D Inverting Input Channel D.
OUT D Output Channel D.
Not applicable 13, 16
Not Internally Connected.
Not applicable
EPAD
Exposed Pad. The exposed pad must be connected to VŠ.
Rev. G | Page 8 of 25
09646-104
UT A
–IN A
+IN A
OUT B
–IN B
+IN B
ADA4610-2
TOP VIEW
(Not to Scale)
Figure 4.
ADA4610-2
Pin Configuration, 8-Lead SOIC (R Suffix)
OUT A
–IN A
+IN A
OUT B
–IN B
+IN B
2
3
4
ADA4610-2
TOP VIEW
(Not to Scale)
09646-102
Figure 5.
ADA4610-2
Pin Configuration, 8-Lead MSOP (RM Suffix)
NOTES
1. THE EXPOSEDPAD MUST BE
CONNECTEDTO V–.
OUT A
–IN A
+IN A
OUT B
–IN B
+IN B
09646-105
4
1
2
6
5
8
ADA4610-2
TOP VIEW
(Not to Scale)
Figure 6.
ADA4610-2
Pin Configuration, 8-Lead LFCSP (CP Suffix)
ADA4610-2
Pin Function Descriptions, 8-Lead SOIC, 8-Lead MSOP, and 8-Lead LFCSP
Pin No. Mnemonic Description
1 OUT A Output Channel A.
2 ŠIN A Inverting Input Channel A.
3 +IN A Noninverting Input Channel A.
4 VŠ Negative Supply Voltage.
5 +IN B Noninverting Input Channel B.
6 ŠIN B Inverting Input Channel B.
7 OUT B Output Channel B.
8 V+ Positive Supply Voltage.
EPAD Exposed Pad for the 8-Lead LFCSP (CP Suffi
x). The exposed pad must be connected to VŠ.








Rev. G | Page 7 of 25
PIN CONFIGURATIONS AND
FUNCTION DESCRIPTIONS
NIC
–IN
+IN
NIC
OUT
NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
ADA4610-1
TOP VIEW
(Not to Scale)
09646-101
Figure 2.
ADA4610-1
Pin Configuration, 8-Lead SOIC (R Suffix)
ADA4610-1
Pin Function Descriptions, 8-Lead SOIC
Pin No.
Mnemonic
Not Internally Connected
2 ŠIN Inverting
Input
3 +IN Noninverting
Input
4 VŠ Negative
Voltage
6 OUT Output
7 V+ Positive
Voltage
09646-100
OUT
+IN
–IN
ADA4610-1
TOP VIEW
(Not to Scale)
Figure 3.
ADA4610-1
Pin Configuration, 5-Lead SOT-23 (RJ Suffix)
ADA4610-1
Pin Function Descriptions, 5-Lead SOT-23
Pin No.
Mnemonic
1 OUT Output
2 VŠ Negative
Voltage
3 +IN Noninverting
Input
4 ŠIN Inverting
Input
5 V+ Positive
Voltage






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